The invention relates generally to the field of electronic circuit design, and in particular to techniques for improving speed in a digital logic circuit, for example, a digital logic flip-flop circuit.
The Semi-Dynamic Flip-Flop (SDFF) is one of the high performance flip-flops based on the hybrid concept. In part due to its size, low clock-to-output delay, negative set-up time, and simple topology, it is considered to be one of the fastest flip-flops today. However, the SDFF is susceptible to a hazard condition, when both the input and output are at a high logic value.
FIG. 1 shows a schematic circuit diagram of a typical prior art SDFF. The data input is D 312, the clock signal is CLK0314, and the outputs are Q 316 and Qbar 317. The two inverters inv5318 and inv6319 are a xe2x80x9ckeeperxe2x80x9d circuit which maintains the value of output Qbar 317 and hence output Q 316. A transparency window for the SDFF is given by the propagation delay of the two inverters, inv1350 and inv2352, and the NAND gate 354. The internal node X 320 of the first stage 330 of the SDFF is set to a high logic level (H), when the clock CLK0314 is at a low logic level (L), i.e., the first stage 330 is pre-charged. When the input signal D 312 is H, node X 320 transitions from H to L in the transparency window where both CLK0314 and S 356 are H (transistors Mn1346, Mn2344, and Mn3342 are on). The second stage 332 captures the transition on node X 320 generated by the first stage 330 and produces output Q 316. In this case node X 320 sets output Q 316 to H via transistor Mp2374. If input D 312 is L, Mn2344 is off and node X 320 remains high during the transparency window. With node X 320 at H, output Q 316 is set at L during the transparency window (transistors Mn4370 and Mn5372 are on).
FIG. 2 is an example timing diagram for the SDFF schematic circuit diagram of FIG. 1 showing a glitch in the output. The timing diagram shows the clock signal CLK0410 representing the CLK0314 in FIG. 3. D414, X 416, and Q 418 show the signals for D 312, node X 320, and Q 316 in FIG. 3 respectively. From FIG. 2, after the rising edge 430 of CLK0410 and with D 414 set to L, X 416 remains at H and output Q 418, due to transistors Mn4370 and Mn5372, transitions from H to L 434. After another rising edge 440 of CLK0410 and with D 414 at H, X 416 transitions from H to L 442 due to transistors Mn1346, Mn2344, and Mn3342 turning on. Next output Q 418 transitions from L to H 444 due to transistor Mp2374. Thus the L to H transition of output Q, e.g., 444, is done using in effect an inverting intermediate node X 320, while the transition of output Q, e.g., 434, from H to L is done directly via nMOS transistors and avoids the slower pMOS transistors. The SDFF is used where the time critical output transitions are from L to H, e.g., 444, on output Q 316, and thus the node X transition, e.g., H to L 442, is important.
However, the asymmetrical transition times of the SDFF lead to a xe2x80x9cstatic-one-hazardxe2x80x9d at the output Q when both input D and output Q are H. In FIG. 2, before the rising edge 450 of the CLK0410, X 416 is set (or reset) to H by transistor Mp1340. Because the first stage 330 has a non-zero propagation delay from the time of the rising clock edge 450 to the time X 416 transitions from H to L 454, the second stage 332 uses the previous X (H). Hence during the time window between the rising edge 450 of the clock CLK0410 and the falling edge 454 of X 416, both Mn4370 and Mn5372 in FIG. 1 are on and the output Q 316 is pulled to low logic level (e.g., transition 452). After the propagation delay, i.e., the falling transition 454 of X 416, the transistor Mp2372 turns on (and Mn4370 turns off), and the output Q 316 is pulled to H (e.g., transition 456). Thus a glitch 462 is caused on the output Q 418 (and Qbar 420) and makes the use of the SDFF hazardous. In addition the glitch consumes power unnecessarily, as output Q 316 should not change, since input D 312 has not changed. Hence some improved flip-flop is needed that has faster or substantially the same speed as the SDFF without the hazard.
There is also a problem of power consumption and increased delay due to the unconditional keepers of the SDFF (back-to-back inverters, inv3360 and inv4362, and back-to-back inverters, inv5318 and inv6319, of FIG. 1). The keeper is used to hold the value of a dynamic node, e.g., node X 320 or out put Q 316, that would otherwise be in high impedance and thus sensitive to leakage current effects and noise. The problem is that in order to change the value of the dynamic node, the keeper has to be overpowered (two keepers, in the case of the SDFF), i.e., the output logic level of the keeper needs to be switched, which increases power consumption and delay. From FIG. 2 it is necessary to fight the keepers on every change of node X 416, e.g., transitions 454, 472, and 442, and on every change of output Q 418, e.g., transitions 452, 456, 434, and 444. Hence while the function of the keeper adds to the robustness of the flip-flop, it introduces delay or slow down of the flip-flop.
Therefore with the problems of a hazard, delay, and power consumption with the SDFF, there is a need for an improved flip-flop with less problems. In addition there is a need for a flip-flop that has the robustness provided by the keeper circuit, but with improved speed.
The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment of the present invention allows for the combining of the evaluation stage with one or more external logic functions.
Broadly the present invention provides a method for conditionally maintaining a logic level of a node in flip-flop circuit. During a first part of a periodic time interval, the logic level of the node is maintained by feeding back to the node the logic level after two inversions. Next, and during a second part of the periodic interval, the logic level of the node is not maintained by disconnecting the feeding back to the node.
In another aspect of the present invention a conditional keeper circuit for conditionally maintaining a logic level of a node in flip-flop circuit is provided. The flip-flop circuit includes a pre-charged stage coupled to an evaluation stage. The conditional keeper circuit includes: an inverter circuit connected to the node; an inverted tri-state circuit connected to the inverter circuit and to the node; and a control circuit that sends a signal to set said inverted tri-state circuit to a high impedance state for a fixed time period.
Yet another aspect of the present invention comprises a system for improving speed in a hybrid type flip-flop is provided. The system includes, a pre-charge stage for determining a pre-charge stage output depending upon a data input during a first part of a transparency window. The pre-charge stage includes a first conditional keeper for keeping the pre-charge stage output. And an evaluation stage for evaluating the pre-charge stage output to produce a data output during a second part of the transparency window. The evaluation stage includes a second conditional keeper for keeping the data output. And when outside of the transparency window, either the first conditional keeper is operating like an unconditional keeper or the second conditional keeper is operating like an unconditional keeper.
The present invention also comprises a method for reducing delay in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node. First, a first keeping circuit of the pre-charged stage is disconnected in at least a first portion of a transparency window, where the first keeping circuit maintains a first logic level on the internal node. Next, the internal node is set to a second logic value after the disconnecting the first keeping circuit; Optionally, a second keeping circuit of the evaluation stage is disconnected in at least a second portion of the transparency window, where the second keeping circuit maintains a third logic level on an output of the evaluation stage. Lastly, the output is set to a fourth logic level based on the second logic value after the disconnecting the second keeping circuit.
A further aspect of the present invention comprises a system for improving performance of a hybrid type flip-flop. The system includes a pre-charge stage for receiving a data input and setting an internal node and an evaluation stage for setting a data output, where the evaluation stage is connected to the pre-charge stage by the internal node. The evaluation stage includes a plurality of NAND gates, where the data output is feedback into a NAND gate of the plurality of NAND gates.
In another embodiment of the present invention a method for combining an evaluation stage of a hybrid flip-flop coupled to external digital logic circuitry is provided, where the evaluation stage includes a plurality of NAND gates. First, the external logic gates in the external digital logic circuitry are identified. Next, a Boolean logic minimization is performed using the external logic gates and the plurality of NAND gates. And lastly, the evaluation stage and the external logic gates are combined.
These and other embodiments, features, aspects and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings.